巴西专利BR112013033613A2 high-performance millimeter-wave / 60 ghz glass-based frame antennas and methods of producing them

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专利摘要:
STRUCTURE ANTENNAS IN WAVE-MM / 60 GHZ BASED ON HIGH GLASS PERFORMANCE AND METHODS OF PRODUCING THE SAMEThe present invention relates to a high-performance MM / 60 GHz wave antenna and the high-performance, glass-based MM / 60 GHz wave antenna includes cavities arranged on a phase antenna substrate (PAA). The cavities are arranged below the flat antenna elements. Emitting tracks are arranged on the PAA substrate opposite the flat antenna elements and the sending tracks, the cavities, and the flat antenna elements are vertically aligned.
公开号:BR112013033613A2
申请号:R112013033613-7
申请日:2012-04-27
公开日:2020-08-04
发明作者:Telesphor Kamgaing
申请人:Intel Corporation；
IPC主号:

专利说明:

Invention Patent Descriptive Report for "STRUCTURE ANTENNAS IN MILIMETRIC WAVE / 60 GHZ HIGH
GLASS-BASED PERFORMANCE AND METHODS OF PRODUCING THE SAME ". 5 Technical Field The modalities described refer to phased-structure antenna substrates for packaged radio frequency integrated circuits and methods of forming the substrates. Brief Description of the Drawings In order to understand the way in which the modalities are obtained, a more particular description description of the various modalities briefly described above will be illustrated by reference to the attached drawings, which illustrate modalities that are not necessarily drawn to scale and should not be Some modalities will be described and explained with specificity and additional details through the use of the attached drawings in which: Figure 1 is a top plan view of a radio frequency antenna chip integrated circuit device in structure phase vertically integrated according to an exemplary modality; Figure 2 is an elevated perspective view of a vertically integrated frame radio frequency antenna chip integrated circuit device assembled in a secondary low cost package according to an embodiment; Figure 3 is an elevated cross-sectional view of the vertically integrated radio frequency antenna chip integrated circuit device assembled in a secondary low-cost package illustrated in Figure 2 and taken along the line in cross section 3 - 3 according to a modality; Figure 4 is a detailed cross-sectional view of the vertically integrated radio frequency antenna chip integrated circuit apparatus assembled in a low cost package.
secondary illustrated in figure 3 according to an embodiment; Figure 5 is a top cross-sectional view of a low loss phase structure antenna according to an exemplary embodiment; 5 Figures 5 to 5h are elevated cross-sectional views of the low-loss phase structure antenna shown in Figure 5 during processing according to several modalities; Figure 5j is a sectional perspective view and partial detail of the elevation of the wire structure of the PAA antenna illustrated in Figure 5 during processing according to an exemplary embodiment; Figure 5f-1 is a sectional perspective view and partial detail of the elevation of the wire structure of the PAA antenna shown in Figure 5 during processing according to an exemplary embodiment; Figures 5k, 5m, and 5n are plan views of the exposed top layer, of the low loss phase structure antenna illustrated in figure 5 according to example modalities; Figure 6 is a detailed cross-sectional view of the top, of the low loss phase structure antenna 600 according to an exemplary model; Figure 6d is an elevated cross-sectional view of a top portion of the low loss phase structure antenna illustrated in Figure 6 during processing according to an exemplary embodiment; Figure 7 is a detailed cross-sectional view of the top, of the structure antenna in low loss phase, according to an exemplary mode; Figure 7d is an elevated cross-sectional view of the top portion of the low loss phase structure antenna shown in Figure 7 during processing according to an exemplary embodiment; Figure 8 is a detailed cross-sectional view of the top, of the low-loss phase structure antenna according to an exemplary mode;
Figure 9 is an exploded perspective view of the wire structure of a vertically integrated radio frequency antenna chip integrated circuit chip apparatus that includes the direct silicon RFIC chip path that is mounted on the plate as a secondary low-cost package; Figure 10 is an elevated cross-sectional view of a chip package that includes a phased-structure antenna substrate with cavities according to an exemplary embodiment; Figure 11 is a process and method flow diagram according to an exemplary embodiment; e Figure 12 is a schematic drawing of a computer system according to a modality.
Detailed Description Processes are described where stamping of radiofrequency integrated circuit through silicon pathway (TSV RFIC) is mounted to antenna substrates of phased structure.
The phased-structure antenna substrates have cavities arranged below the individual antenna elements.
Reference will now be made to drawings in which similar structures can be provided with similar reference designation suffixes.
In order to show the structures of various modalities more clearly, the drawings included here are diagrammatic representations of integrated circuit structures.
Thus, the current appearance of the integrated circuit structures manufactured, for example, in a photomicrograph, may appear different and still incorporate the claimed structures of the illustrated modalities.
Furthermore, the drawings can only show the useful structures to understand the illustrated modalities.
Additional structures known in the art may not have been included to maintain the clarity of the drawings.
Figure 1 is a top plan view of a vertically integrated phase-integrated radio frequency antenna chip device 100 according to an exemplary embodiment. A phase antenna substrate (PAA) 110 is illustrated in shape simplified with a structure of 4 X 4 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 123, 124, 125, and 126 flat antenna elements. The PAA elements are positioned in rows of 4 - 4 - 4 - 4. In said modality, 5 eight of the PAA elements are receiving elements and 8 PAA elements are transmitting elements.
In one embodiment, the number of PAA elements is in a range from 4 to 64. In one embodiment, the number of PAA elements is 36 in a 6 X 6 structure in which 18 PAA elements are receiving elements and 18 elements of PAA are transmitting elements.
In one embodiment, the number of PAA elements is 64 in the 8 X 8 structure in which 32 PAA elements are receiving elements and 32 PAA elements are transmitting elements.
In a fashion, the 64 elements are divided into many structures.
For example, four 4 x 4 structures are configured, each from two antenna elements are configured to receive and two are configured to transmit.
In one embodiment, a 32-element in-phase frame antenna is split into many structures.
For example, two 4 x 4 structures are configured, each from two antenna elements are configured to receive and two are configured to transmit.
Direct silicon stamping (TSV) 128 is illustrated in dotted lines below the PAA 110 substrate and the TSV 128 stamping is vertically integrated (Direction Z) with the PAA 110 substrate. In one embodiment, the TSV stamping 128 includes active and passive circuits in semiconductor material.
For example, the TSV 128 stamping is part of a processor manufactured by Intel Corporation of Santa Clara, California.
In one embodiment, the TSV 128 stamping contains a chip system (SoC) 128 such as a double-processor microelectronic device.
In one embodiment, the TSV 128 stamping includes a hybrid digital processor device and radio frequency integrated circuit (DP-RFIC) 128. In one embodiment, the TSV 128 stamping includes a SoC 128 that includes a DP and a graphics hybrid ( DP-GIC) such as the Sandy Bridge type name and manufactured by Intel Corporation.
In one embodiment, the TSV 128 stamping is a radio frequency integrated circuit (RFIC) TSV stamping 128. It can be seen that the TSV RFIC 128 stamping has a coverage area that is smaller than that of the PAA 110 substrate. and that of the 5 PAA 110 substrate is symmetrically arranged above the TSV RFIC 128 embossing. As illustrated, the quadrilateral symmetry is seen between the PAA 110 substrate and the TSV RFIC 128 embossing. "Quadrilateral Symmetry" can be understood to be that which starts at the XY center of the apparatus 100, a PAA element that is found can be balanced by finding an analog PAA element when it moves in the opposite direction along the same line taken.
Although the flat antenna elements are illustrated in quadrilateral symmetry, they can be positioned in other configurations such as radial symmetry.
The flat antenna elements can also be positioned as in rows of 3 - 5 - 5 - 3, which is a 16-element structure that is not a perfect geometry square although 16 is a perfect numerical square.
The flat antenna elements can also be positioned as in rows of 4 - 6 - 6 - 6 - 6 - 4, which is a 32-element structure that is not a perfect square.
Because it is capable of placing the TSV RFIC 128 stamping directly below the PAA 110 substrate, it is useful to achieve more uniform impedances, signal attenuations and phase delay between them.
Uniform impedances can mean that the device 100 can operate in such a way that no significant difference in line impedance can be observed when comparing the operation of any two antenna elements on the PAA substrate in a given application.
In addition to being able to arrange the TSV RFIC 128 stamping directly below the PAA 110 substrate, a smaller useful device is achieved that facilitates the miniaturization of the package.
Figure 2 is an elevated perspective view of a vertically integrated phase-frame radio frequency antenna chip integrated apparatus 200 mounted in a secondary low-cost package 230 (also referred to as plate 230) according to a mo-
dality. In one embodiment, plate 230 is a direct chip (DCA) 230 plate. Where a secondary low-cost package 230 is used, removing RF / millimeter wave signals allows for a broader step to lower the frequency of signals on plate 230. This makes it possible to attach first-level stamping interconnectors such as collapsed chip connection protrusions (C4) directly to the plate
230. The apparatus 200 is illustrated in a partial wire structure in order to illustrate the positioning of a TSV RFIC 228 stamping arranged below (Z-direction) a PAA 210 substrate. A 4 x 4 flat antenna PAA configuration is arranged in the substrate of PAA 210, one of which is indicated with reference numeral 211. The TSV RFIC 228 stamping is illustrated with 16 direct silicon pathways that are in groups of four, or that are indicated with reference numeral 232. Each of 16 TSVs 232 are coupled to a corresponding flat antenna element such as the flat antenna element 211. Additional TSVs not shown in figure 2 can be used to provide adequate electrical ground reference for the 16 TSVs 232 signals. The TSV stamping RFIC 228 is a flip-chip mounted to a plate directly attached to the chip (DCA) 230 by a plurality of electrical protrusions 234, one of which is indicated with the reference numeral 234. Electrical protrusions 234 are protrusions of first level interconnection such as C4 protrusions that are attached to the active side of a stamping. As illustrated, electrical protrusions are configured in a 12 X 12 structure, but another protrusion count can be used where necessary. Additional stabilizing dampers, one of which is indicated with reference numeral 236, are positioned between the PAA 210 substrate and the secondary low-cost package 230. The stabilizing dampers 236 connect the space between the PAA 210 substrate and the package secondary low cost 230 and adds mechanical stability and thermal stress to the device 200 and the secondary low cost package 230. In one embodiment, electrical grounding capabilities are achieved through stabilizer dampers 236 for at least the PAA 210 substrate and the TSV RFIC 228. Figure 3 is an elevated cross-sectional view of the vertically integrated 5-phase radio frequency antenna chip integrated circuit device 300 mounted on the direct chip fixing plate 230 shown in figure 2 and taken along the line in cross section 3 - 3 according to a modality.
The apparatus 300 includes the PAA 210 substrate and the TSV RFIC 228. Additionally, the secondary low-cost package 230 is coupled to the PAA substrate 210 by rear electrical protrusions 238. A plurality of TSVs can be seen in the TSV RFIC 228, two of which are indicated with reference numeral 232. Other structures can be seen in figure 3. Where the TSV RFIC 228 is an active RF device with RF and millimeter wave signals being transmitted through TSVs to the phase structure antenna, lower frequency functions are separated from the PAA 210 substrate and contained in the secondary low cost package 230. The aforementioned vertical integration system reduces signal congestion and facilitates a small factor of shape that is limited by dimensions of the PAA 210 substrate. In one embodiment, the PAA 210 substrate operates in the 60 GHz sphere while the low secondary cost package 230 operates at lower frequencies.
In one embodiment, the 60 GHz or millimeter wave phase or millimeter wave structure including the flat antenna elements 211, 212, 213, and 214 is mounted to the TSV RFIC 228 millimeter wave (millimeter wave) that requires a Gb transfer rate / s over a wireless link.
In one embodiment, the wireless link is to a wireless screen from a wireless transmission for uncompressed high definition (HD) video. Figure 4 is a detailed elevated cross-sectional view of the vertically integrated radio frequency antenna chip integrated circuit apparatus mounted on the direct chip attachment plate shown in Figure 3 according to an embodiment.
Apparatus 400 includes the PAA 210 substrate and TSV RFIC 228. Apparatus 400 is mounted on the secondary low-cost package 230.
The PAA 210 substrate is illustrated with two occurrences of the flat antenna elements 212 and 213 which are exposed through a frame mask 240. Below the flat antenna elements 212 and 213 are corresponding cavities 255 that allow a useful increase in width bandwidth.
In one embodiment, the metallic layer 242 is arranged on the PAA 210 substrate to increase the bandwidth of the antenna.
Electrical contact between the TSV RFIC 228 and the antenna elements is made through at least one trace 244 which is coupled to the TSVs 232 through the rear protrusions 238. The electrical coupling of the antenna elements 212 and 213 through the PAA substrate 210 is performed either by direct or inductive coupling.
In one embodiment, the PAA substrate 210 includes a first dielectric layer 252 and a second dielectric layer 254 that corresponds to the first dielectric layer 242. In one embodiment, the first dielectric layer 252 has a higher dielectric constant than the second dielectric layer 254. The second dielectric layer 254 is a glass material.
In one embodiment, the first dielectric layer 252 is a glass material.
In one embodiment, the first dielectric layer 252 is an organic material.
In one embodiment, the first dielectric layer 252 is a ceramic material.
In one embodiment, the first dielectric layer 252 is an inorganic material such as alumina.
The second dielectric layer 254 is also configured with a plurality of cavities 255 each of which is aligned below an antenna element such as antenna elements 212 and 213. It can be seen that the second dielectric layer 254 has a thickness 256 that extends between the antenna elements and the metal layer 242. Below each antenna element 212, cavity 255 reduces the effective thickness of the second dielectric layer 254 from the remaining thickness 257 and any substance such as air that is disposed in a cavity 255 In one mode, cavity 255 is open to the external environment (see figure 5j) so that changes in the external environment can allow cavity 255 to breathe in exchange for external pressures.
TSV RFIC 228 includes an active device layer 250 that displays an active surface 227. The metallization is indicated in part with a top connection pad 251. The active surface 227 is opposite to a back embossing surface 229. The metallization 251 can also be referred to as the silicon rear end 251. In one embodiment, metallization layer 251 has several metallization layers such as metal-1 (Ml) to Ml 2 depending on a particular need for TSV RFIC 228 In any event, TSVs 232 originate in a metallization layer 251 and penetrate TSV RVIC 228 into the rear surface 229 in order to allow TSV RVIC 228 to communicate with the antenna elements of the PAA 210 substrate. TSVs 232 make electrical contact with the rear protrusions 238 and are therefore coupled to the antenna elements 212 and 213. The secondary low-cost package 230 is coupled to the TSV RFIC 228 by the electrical protrusions 234 and the subs PAA 210 treatment by stabilizer dampers 236 (see figure 3). In one embodiment, the secondary low cost package 230 is a first level chip fixing substrate and a discharge surface 231 is provided as a second level chip fixing substrate.
In one embodiment, the discharge surface 231 is a discharge grid structure surface 231. In one embodiment, the discharge surface 231 is a pin grid structure surface 231. Figure 5 is a sectional view. detailed cross-section of the top, of the low-loss phase 500 structure antenna according to an exemplary model.
The antenna 500 is part of a substrate of PAA 510. The substrate of PAA 510 is illustrated with four occurrences of flat antenna elements 511, 512, 513, and 514 that are exposed through a structure mask 540 that can be about 20 micrometer (µm) thick.
In one embodiment, the structure mask 540 is a passivation layer that encapsulates the flat antenna elements.
As illustrated, the flat antenna elements 511, 512, 513, and 514 are exposed to a top surface but they are covered on the bottom surface with a second dielectric layer 554.
Cavities 555 are arranged on the PAA 510 substrate below each of the flat antenna elements to facilitate the useful increase in bandwidth.
In one embodiment, the metallic layer 542 is arranged on the PAA 510 substrate to increase the bandwidth of the antenna. 5 Electrical contact between the TSV RFIC and the antenna elements 511, 512, 513, and 514 is made through at least one trace 544 that must be coupled to the TSVs through rear protrusions 538 that are arranged between the TSV RFIC and the substrate of PAA 510. Trace 544 can be a ground plane with an opening 580 that facilitates inductive coupling between a trace emitter 545 and a corresponding flat antenna element 514. It can be seen that trace emitter 545 , the cavity 555, and the flat antenna element are vertically aligned.
Trace 544 is protected by a solder resistor 541 which can be about 20 µm thick.
Electrical protrusions 538 are provided through solder resistor 541 to couple the PAA 510 to a device such as a TSV RFIC.
The electrical coupling of the antenna elements 511, 512, 513, and 514 through the PAA substrate 510 is accomplished by inductive coupling where a trace emitter 545 emits EM waves in the antenna elements 511, 512, 513, and 514 through not only of a high k dielectric 552 such as a glass material but also a lower k dielectric layer 554 that includes the cavities 555. It can be seen that the second dielectric 554 has a thickness 556 that extends between the antenna elements and trace 544. Below each antenna element 511, 512, 513, and 514, cavity 555 reduces the effective thickness of a second dielectric 554 to a remaining thickness 557 and any ambient substance such as air that is disposed in the cavity 555. In one embodiment, cavity 555 is open to the external environment so that changes in the external environment can allow cavities 555 to breathe on changes in external pressures.
The lower k dielectric layer 554 can also be a glass material.
In one embodiment, the first dielectric layer 652 has an Er of about 5.5, a tan delta of about 0.001, and a thickness of about 100 µm, and the lower k dielectric layer 654 has an Er from about 2.0 to 2.5, a tan delta of about 0.001, and a thickness from about 250 µm to about 400 µm.
Figures 5 to 5h are elevated cross-sectional views of the low-loss phase structure antenna shown in Figure 5 during processing according to various modalities.
Figure 5a is an elevated cross-sectional view of the top of the low-loss phase structure antenna shown in Figure 5 during manufacture according to an exemplary model.
The material that will become the second dielectric 554 is superimposed with a metallic material that will become the antenna elements 511 such as by electroplating without electrode.
Figure 5b is an elevated cross-sectional view of the PAA substrate illustrated in 5a after further processing according to an embodiment.
A structure of flat antenna elements 511, 512, 513, and 514 has been standardized from the metallic material illustrated in figure 5a to form the phase structure antenna.
In figure 5c, further processing was carried out by fixing the passivation layer 540 to protect the PAA elements 511, 512, 513, and 514. In one embodiment, the structure mask 540 is standardized to expose the PAA elements 511 -514 from above (Direction Z). In figure 5d, further processing was performed by forming a plurality of cavities 555 below each of the PAA elements 511, 512, 513, and 514. Processing can be carried out such as laser drilling to form cavity 555. In one mode, drilling with a drill tip is performed.
In one embodiment, laser drilling is performed.
In one embodiment, the first drill with a drill tip is performed, followed by a laser drill finish.
In one mode, shallow 592 channels are formed between adjacent cavities to facilitate adjustments to the ambient condition.
Figure 5e is an elevated cross-sectional view of the PAA substrate shown in Figure 5 during processing according to an embodiment.
It is observed here that the second dielectric 554 is produced
separately from a first dielectric, followed by joining them together to form the PAA 500 substrate illustrated in figure 5. A first dielectric 552 was superimposed with metallic material that will form part of line 544. In figure 5f , the processing was performed to standardize the trace 544 and to electrically couple both traces by forming electrical paths filled between them. Additional processing was also carried out to assemble both forms of emitting tracks 545 that correspond to the plurality of PAA elements that are attached to the second dielectric 554 seen in figure 5d. Figure 5f-1 is a cross-sectional view of the first dielectric layer 552 during processing in contrast to the structure shown in Figure 5f. A first cavity of dielectric layer 555.1 is formed incidental to the formation of the path so that cavity 555.1 increases cavity 555 illustrated, for example, in the second dielectric layer 554 in figure 5d. In figure 5g, a solder resistor 541 was formed over the emitting traces 545 and the trace 544. In figure 5h, the standardization of the solder resistor 541 was performed to expose the emitting traces 545 as well as the electrical protuberances 538 were formed. to communicate with the dash
544. Figure 6 is a detailed cross-sectional view of the top of the low-loss phase 600 structure antenna according to an exemplary model. Antenna 600 is part of a PAA 610 substrate. The PAA 610 substrate is illustrated with four occurrences of flat antenna elements 611, 612, 613, and 614 that are exposed through a frame structure 640 that can be about 20 µm in thickness. In one embodiment, the structure mask 640 is the passivation layer that encapsulates the flat antenna elements from below (within the substrate 610). As illustrated, the flat antenna elements 511, 512, 513, and 514 are exposed on the top surface and they are also exposed on the bottom surface of them by their corresponding cavities 655.
Cavities 655 are arranged on the PAA 610 substrate below each of the flat antenna elements to facilitate useful increase in bandwidth.
As illustrated, the 655 cavities extend vertically to expose the flat antenna elements.
In one embodiment, the metal layer 642 is arranged on the PAA 610 substrate to increase the antenna bandwidth.
The electrical contact between the TSV RFIC and the antenna elements 611, 612, 613, and 614 is made through at least one trace 644 that must be coupled to the TSVs through rear protuberances that are arranged between the TSV RFIC and the substrate of PAA 610. Trace 644 can be a ground plane with an opening 680 that facilitates inductive coupling between a trace emitter 645. Trace 644 is protected by a solder resistor 641 which can be about 60 µm thick.
Electrical protrusions 638 are provided through solder resistor 641 to couple the PAA 610 to a device such as the TSV RFIC.
The electrical coupling of the antenna elements 611, 612, 613, and 614 through the PAA substrate 610 is performed by inductive coupling where a trace emitter 645 that emits EM waves on the antenna elements 611, 612, 613, and 614 through a high k dielectric 652 such as a glass material through cavities 655 in a lower k dielectric layer 654. It can be seen that the second dielectric layer 654 has a thickness 656 that extends between the elements antenna and trace 644. Below each antenna element 611, 612, 613, and 614, cavities 655 reduce the effective thickness of the second dielectric layer 654 to essentially zero remaining thickness of the second dielectric layer 654 but the same includes any ambient substance such as air that is disposed in cavity 655. In one embodiment, cavity 655 is opened to the external environment so that changes in the external environment can allow cavities 655 to breathe with the change in external pressures at.
The lower k dielectric layer 654 can also be a glass material.
In one embodiment, the first dielectric layer 652 has an Er of about 5.5, a tan delta of about 0.001, and a thickness of about 100 µm, and the lower k dielectric layer 654 has an Er from about 2.0 to 2.5, a tan delta of about 0.001, and the thickness from about 250 µm to about 400 µm.
Figure 7 is a detailed cross-sectional view of the top 5 of the low loss phase 700 structure antenna according to an exemplary model.
Antenna 700 is part of a PAA 710 substrate. The PAA 710 substrate is illustrated with four occurrences of flat antenna elements 711, 712, 713, and 714 that are arranged within cavities 755 of the lower k dielectric layer 754 Cavities 755 are arranged on the PAA 710 substrate and each of the flat antenna elements is arranged in cavities 755 to facilitate the useful increase in bandwidth.
In one embodiment, the metallic layer 742 is arranged on the PAA substrate 710 to increase the bandwidth of the antenna.
The electrical contact between the TSV RFIC and the antenna elements 711, 712, 713, and 714 is made through at least one trace 744 that must be coupled to the TSVs through rear protuberances that are arranged between the TSV RFIC and the substrate of PAA 710. The trace 744 can be a ground plane with an opening 780 that facilitates inductive coupling between a trace emitter 745. The trace 744 is protected by a welding resistor 741 which can have a thickness of about 20 µm.
Electrical protrusions 738 are provided through the solder resistor 741 to couple the PAA 710 to a device such as the TSV RFIC.
The electrical coupling of the antenna elements 711, 712, 713, and 714 through the PAA substrate 710 is performed by inductive coupling where a trace emitter 745 emits EM waves over the antenna elements 711, 712, 713, and 714 through not only a high k dielectric 752 such as a glass material but also a lower k dielectric layer 754 that includes cavities 755. It can be seen that a second dielectric 754 has a thickness 756 that extends between the top (outside) of the PAA substrate 710 and the dash 744. Below each antenna element 711, 712, 713, and 714, the cavity 755 reduces the effective thickness of a second dielectric 754 to a remaining thickness 757 and any substance such as air that is disposed in cavity 755. In one embodiment, cavity 755 is opened to the external environment so that changes in the external environment can allow cavities 755 to breathe with the change in external pressures. The lower k dielectric layer 754 can also be a glass material.
In one embodiment, the first dielectric layer 752 has an Er of about 5.5, a tan delta of about 0.001, and the thickness of about 100 µm and the lower k dielectric layer 754 has an Er from about 2.0 to 2.5, a tan delta of about 0.001, and the thickness from about 250 µm to about 400 µm.
Figure 8 is a detailed cross-sectional view of the top, of the low-loss phase structure antenna 800 according to an exemplary model.
The antenna 800 is part of a PAA 810 substrate. The PAA 810 substrate is illustrated with four occurrences of flat antenna elements 811, 812, 813, and 814 that are exposed through a structure mask 840 that can be about 20 µm in thickness.
Cavities 855 are arranged on the PAA 810 substrate below each of the flat antenna elements to facilitate the useful increase in bandwidth.
In one embodiment, the metallic layer 842 is arranged on the PAA substrate 810 to increase the bandwidth of the antenna.
The electrical contact between the TSV RFIC and the antenna elements 811, 812, 813, and 814 is made through at least one trace 844 that must be coupled to the TSVs through rear protuberances that are arranged between the TSV RFIC and the substrate of PAA 810. The trace 844 can be a ground plane with an opening 880 that facilitates via coupling between a trace emitter 845. The contact path 890 passes through the opening in trace 844 and makes contact with the antenna element 814. Consequently In said embodiment, the antenna elements 814 are contacted via the contact path 890 from the trace emitter 845. The trace 844 is protected by a solder resistor 841 which can have a thickness of about 20 µm.
Electrical protrusions 838 are provided through the solder resistor 841 to couple the PAA 810 to a device such as the TSV RFIC. Electrical contact of antenna elements 811, 812, 813, and 814 through the PAA substrate 810 is made via contact 890. It can be seen that a second dielectric 854 has a thickness 856 that extends between the elements antenna and the metallic layer
842. Below each antenna element 811, 812, 813, and 814, cavity 855 reduces the effective thickness of a second dielectric 854 to a remaining thickness 857 and any substance such as air that is disposed in the cavity 855 In one embodiment, cavity 855 is open to the external environment so that changes in the external environment can allow cavities 855 to breathe with the change in external pressures. Figure 6d is an elevated cross-sectional view of a portion of the top of the low loss phase frame antenna 600 shown in Figure 6 during processing according to an exemplary embodiment. Processing of the PAA 600 antenna can be similar to that of the PAA 500 antenna illustrated in figures 5a-5c with a variation of making the cavities 655 extend to expose the PAA elements 611, 612, 613, and 614 from below (inside of the PAA 610 substrate). The engraving or perforation of the 655 cavities, or a combination of them, is carried out with the care of leaving the lateral edges (XY Directions) of the PAA elements fixed in a 654 second dielectric. The physical drilling process is initiated to form cavity precursors, followed by a laser drilling process that stops at the PAA elements. Figure 7d is an elevated cross-sectional view of the top portion of the low-loss phase structure antenna 700 shown in Figure 7 during processing according to an exemplary embodiment. Processing of the PAA 700 antenna can be similar to that of the PAA 500 antenna illustrated in figures 5a-5c with the variation of forming the cavities 755 followed by the formation of the PAA elements 711, 712, 713, and 714 within the cavities. In a modality of processing, galvanizing or drilling the 755 cavities, or a combination of them,
used.
A metallic film is formed by covering over the topology of the cavities, followed by two directional galvanizations that use the depths of the cavities 755 to protect the PAA elements 711, 712, 713, and 714. The PAA elements 711, 712, 713, and 714 are protected 5 from galvanizing by the depths of cavities 755 and the shallow angle of directional galvanizing.
Other processing methods can be used to form PAA elements 711, 712, 713, and 714 within wells 755. After the formation of PAA elements 711, 712, 713, and 714 within wells 755, a second dielectric layer 754 is inverted and mounted to the first dielectric layer 752 as shown in figure 7. Figure 5j is a sectional perspective view and partial detail of the elevation of the wire structure of the PAA 500 antenna shown in figure 5 during processing according to an exemplary embodiment.
The structure is inverted with respect to the antenna 500 illustrated in figure 5. The processing is in a state that is approximately equal to the structure illustrated in figure 5d except that a detail in cross section is exposed that reveals the two elements of antenna 513 and 514 seen in figure 5. It can be seen that a shallow channel 592 was formed at the base of the second dielectric layer 554. The shallow channel 592 allows the ambient gas to balance within cavities 555 as well as moisture management within them.
In one embodiment, an antenna is tested on a glass substrate.
A first antenna was tested without cavities below the flat antenna elements.
The first antenna tested at 3.6 GHz (where the frequency range in which the input return loss is less than -10dB). A second antenna is tested with the same size and structure configuration as the first antenna.
The second antenna has cavity cover areas that were equal to the areas of the flat antenna elements.
The second antenna had a cavity-forming factor similar to that illustrated in figure 5, but without the structure 542. The size of the coverage area is measured at the junction of trace 544 and the second dielectric layer
554. The second antenna tested at 4.7 GHz. The third antenna is tested with details of the same size and structure as the first antenna. The third antenna has cavity cover areas that were larger than the areas of the flat antenna elements, as illustrated in figure 5j. The third antenna had a cavity-forming factor similar to that illustrated in figure 5, but without the structure 542. The size of the coverage area is measured at the junction of trace 544 and the second dielectric layer 554. The proportion of area of coverage cavity coverage for antenna element was about 1.96. The third antenna tested at 5.1 GHz. Figures 5k, 5m, and 5n are planar views of the exposed layer at the top of the low loss phase structure antenna illustrated in figure 5 according to example modalities. Figure 5k is a top plan view of the PAA 500 substrate shown in Figure 5 according to a modality. The structure of phase structure antenna elements 511-526 is shown on a second dielectric 554 with the cavities 555 shown in dotted lines on a second dielectric layer 554. The cavities 555 are arranged below the structure of structure antenna elements in phase 511-526. The ratio of cavity coverage area to antenna element area is about 1.96 according to one embodiment. Figure 5m is a sectional top plan view of a portion of the PAA substrate shown in Figure 5 according to a modality. The at least one line 544 is shown with the opening 580 at the level of figure 5 where a second dielectric 554 corresponds to at least one line 544. While cavities 555 have an image projected in figure 5k, cavities 555 have a coverage area in at least one stroke
544. Figure 5n is a top plan view in section of a portion of the PAA substrate shown in Figure 5 according to an embodiment. The lower portion of the at least one trace 544 is shown with the cavity cover areas 555 projected thereon. The trace emitter 545 is shown in a dielectric insulator 541 that can be the welding mask material.
Figure 9 is an exploded perspective view of the wire structure of a vertically integrated radio frequency antenna chip integrated circuit 900 apparatus which includes a 928 direct silicon RFIC chip path that is mounted on the plate 930 as well as a secondary low-cost package.
In one embodiment, plate 930 is a DCA package.
In one embodiment, plate 930 includes an embedded passive device 994. As illustrated, apparatus 900 is configured with TSV RFIC 928 and a PAA 910 substrate that includes cavities (not shown) arranged below each flat antenna element.
The PAA 910 substrate is illustrated with 16 antenna elements 911 to 926 in a configuration of 3 - 5 - 5 - 3 (X direction). The TSV RFIC 928 is placed above the secondary low cost package 930 and a passive device 994, in this illustration a folded inductor 994, is embedded in the secondary low cost package 930. In one embodiment, the device includes the substrate of PAA 910, TSV RFIC 928, and also a TSV DP 992. In one embodiment, device 992 is a fast-access local memory such as a solid state drive (SSD) and RF printing 928 is a hybrid printing RF- and DP 928 integrated circuit. In one embodiment, the RF 928 stamping is supported by a hybrid DP-GIC stamping 992. In one embodiment, only the PAA 910 substrate and the TSV RFIC 928 are present.
The 900 device is illustrated in a simplified form that includes metallization of TSV DP 996 that supports the TSV DP 992 and metallization of RFIC 950 that supports the TSV RFIC 928. In one embodiment, the TSV RFIC 928 is inverted compared to the orientation illustrated in figure 9, so that the metallization 950 and the active surface touches the PAA 910 substrate for shorter connections to the 911-926 antenna elements. In one embodiment, the secondary low-cost package 930 is a colorless substrate 930 that includes at least one passive device embedded in it.
The electrical communication between p DP-RFIC 992 and the secondary low cost package 930 is carried out through electrical protrusions.
according to any modality described or otherwise according to the known technique.
As illustrated, DP-RFIC 992, if present, is a 992 flip-chip that is corresponding to the secondary low cost package 930 by using electrical protuberances in accordance with any of the described modalities or otherwise in accordance with the known technique.
Other passive devices can be built into the secondary low cost package according to any technique described in PCT Patent Application No.
PCT / US2010 / 061388, filed on December 20, 2010, the description of which is incorporated herein by reference in its entirety.
Any RF quality capacitors can be positioned within the silicon of the TSV RFIC 928 according to one modality.
As a passive front end module device, at least one RF quality capacitor is positioned inside the TSV RFIC 928 remains within the silicon of the TSV RFIC 928 where it can be manufactured with a high k dielectric material for the useful capacitance and useful small size compared to that of the inductors that can be positioned inside the secondary low cost package 930. Figure 10 is an elevated cross-sectional view of a 1000 chip package that includes an antenna substrate of 1080 phase structure with 1055 cavities according to an exemplary embodiment.
The chip pack 1000 includes an RF stamping 1010. In one embodiment, subsequent TSV digital processor (DP) stamping 1052 is also provided.
A 1072 mounting substrate is also provided as well as the PAA 1080 substrate. In one mode, the 1072 mounting substrate is a DCA 1072 plate. The subsequent TSV stamping 1052 is coupled to the PAA 1080 substrate via RF stamping 1010. The PAA 1080 substrate is illustrated with four occurrences of flat antenna elements 1081, 1082, 1083, and 1084 that are exposed through a frame mask 1086. In one embodiment, the frame mask 1086 is the passivation layer and the antenna elements are covered with it.
In one embodiment, the metallic layer 1088 with openings 1096 is arranged on the PAA 1080 substrate. In one embodiment, an additional metallic layer 1089 is provided to increase the antenna bandwidth.
The ground plane 1088 is coupled to the 1090 stabilizing dampers via the 1092 ground path on the PAA 1080 substrate. Electrical contact between the RF stamping 1010 and the antenna elements is made through at least one emitter. trace 1094. The electrical coupling of the antenna elements 1081, 1082, 1083, and 1084 through the PAA 1080 substrate is performed by opening power from an inductive coupling included through the openings 1096 in trace 1044 and through the cavities 1055 in one second dielectric 1096. In one embodiment, the PAA 1080 substrate includes a first dielectric layer 1098 and a second dielectric layer 1096. In one embodiment, the first dielectric layer 1098 is glass and has a higher dielectric constant than the second layer dielectric 1096 which is also glass.
RF stamping 1010 is coupled to the PAA 1080 substrate through at least one TSV 1057 and at least one trace emitter 1094. The at least one TSV 1057 is for one of the signal and energy and earth functions.
In one embodiment, the RF stamping 1010 TSV signals are transmitted to the phase structure antenna elements, but the lower frequency functions are separated from the PAA 1080 substrate and contained in the 1072 mounting substrate. integration system reduces signal congestion and facilitates the smallest XY form factor that is limited by dimensions of the PAA 1080 substrate. In addition to the signal / energy / ground TSVs 1057, at least one sector of RF stamping 1010 is a shielded sector 1024 by virtue of the shielding TSVs 1026 which forms an enclosure 1026 and a rear side shielding 1028 which forms a lattice cover 1028. It can now be understood that the positions of the RF embossing 1010 and the embossing of DP 1052 can be exchanged and the active surface of the RF 1010 stamping can touch the PAA 1080 substrate.
Figure 11 is a process flow diagram and method 1100 according to an exemplary embodiment.
In 1110, the process includes forming a phased-structure antenna substrate with cavities below flat antenna elements.
It is understood that a first dielectric and a second dielectric are manufactured separately and then assembled.
In an exemplary non-limiting modality, the second substrate 554 is manufactured by a different business entity from that which manufactures the first substrate 552. In a non-limiting process modality, the cavity coverage area is formed less than the area of the flat antenna element in a range from 50% to 99.9%. In a non-limiting process, the cavity coverage area is formed equal to the area of the flat antenna element.
In a non-limiting process modality, the cavity coverage area is formed larger than the area of the flat antenna element in a range from 100.1% to 300%. In a non-limiting process mode, the cavity coverage area is formed larger than the area of the flat antenna element by 196%. In 1120, a method modality includes assembling a direct silicon stamping apparatus and the phased-structure antenna substrate.
In an exemplary non-limiting modality, the TSV RFIC 228, shown in figure 3, is mounted to the substrate of PAA 210. In an exemplary non-limiting modality, the TSV RFIC embossing is assembled with the active surface of the same touching the substrate of PAA.
In 1122, a process modality included mounting or adding the local memory for quick access of TSV to the device.
In 1124, a process modality included assembling or adding a digital silicon processor directly to the device.
In an exemplary non-limiting mode, TSV DP 1052 is added to TSV RFIC 1010 as illustrated in Figure 1000. In 1126, a process includes mounting the TSV RFIC to a PAA substrate so that the electrical coupling is by power supply. gap between TSV RFIC and PAA flat antenna elements.
In terms of
non-limiting exemplary features, the opening feed couples the PAA substrates shown in figures 4, 5, 6, and 7 to the respective RF print.
In 1128, a process includes mounting the TSV RFIC to a PAA substrate 5 so that the electrical coupling is by conductive power between the TSV RFIC and the flat antenna elements of the PAA.
In an exemplary non-limiting modality, conductive feeding is used on the 800 device, illustrated in figure 8. In 1130, the method modality includes testing the device.
In an exemplary, non-limiting modality, the device that essentially consists of the PAA substrate that corresponds to the TSV RFIC is tested before assembling the device in a low-cost secondary package.
For example, a test template may have an electrical contact coverage area similar to that of the TSV RFIC so that the test can be performed without a permanent secondary low cost package attached.
In 1140, a process modality included mounting the device to the plate.
In one embodiment, the card is a low-cost secondary package.
In one embodiment, the card is a DCA card.
In an exemplary, non-limiting modality, the test in 1140 is performed after mounting the device to the low-cost secondary package.
In 1142, a process modality included making at least one passive device on or on the plate.
In an exemplary, non-limiting modality, the folded inductor 994 is manufactured in a low-cost secondary package without core 930 as illustrated in figure 9. In a fashion, the protrusion inductor is positioned between the low cost package secondary and TSV RFIC.
In one embodiment, a stacked track inductor is positioned between the TSV RFIC and at least partially in the secondary low-cost package 930. In 1150, the method modality includes mounting the device to a computer system.
In the exemplary non-limiting modality, the computer system illustrated in figure 12 has features of an antenna element such as any PAA substrate described with cavitation.
below the flat antenna elements in connection with that description.
In an exemplary, non-limiting modality, the assembly of the device to a computer system is carried out where the plate is a foundation substrate. 5 In 1160, the method modality includes operating a method device using the TSV RFIC and PAA device.
In one embodiment, a method 1284 device is operated by a mode apparatus using elements of PAA 1282. Figure 12 is a schematic drawing of a computer system according to one embodiment.
The computer system 1200 (also referred to as the electronic system 1200) as illustrated can incorporate a device that includes the TSV RFIC which corresponds to a PAA substrate with cavities according to any of the various described modes and their equivalents as determined in the description.
An apparatus that includes the TSV RFIC that corresponds to a PAA substrate with cavities is mounted to a computer system.
The computer system 1200 can be a mobile device such as a net-ok computer.
Computer system 1200 can be a mobile device such as a cordless smart phone.
The computer system 1200 can be a desktop computer.
Computer system 1200 can be a portable reader.
The computer system 1200 can be integrated into a car.
The computer system 1200 can be integral to a television.
The 1200 computer system can be integrated with a dvd player.
The 1200 computer system can be integrated with a digital video camera.
In one embodiment, the electronic system 1200 is a computer system that includes a system bus 1220 to electrically couple the various components of the electronic system 1200. The system bus 1220 is a single bus or any combination of buses according to various modalities.
The electronic system 1200 includes a voltage source 1230 that supplies power to the integrated circuit 1210. In some embodiments, the voltage source 1230 supplies power to the integrated circuit 1210 through the system bus 1220.
The integrated circuit 1210 is electrically coupled to the system bus 1220 and includes any circuit, or combination of circuits according to a modality.
In one embodiment, integrated circuit 1210 includes a processor 1212 that can be of any type of apparatus 5 that includes the TSV RFIC that corresponds to a PAA substrate modality with cavities.
As used here, processor 1212 can mean any type of circuit such as, but not limited to, a microprocessor, microcontroller, graphics processor, digital signal processor, or other processor.
In one embodiment, the 1212 processor is the TSV RFIC embedded embossing BBUL described here.
In one embodiment, SRAM modes are found in processor memory caches.
Other types of circuits that can be included in integrated circuit 1210 are a custom circuit or an application specific integrated circuit (ASIC), such as a communication circuit 1214 for use in wireless devices such as cell phones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems.
In one embodiment, processor 1210 includes fast access local memory 1216 such as static random access memory (SRAM). In one mode, processor 1210 includes built-in local quick access memory 1216 as well as built-in dynamic random access memory (eDRAM). In one embodiment, integrated circuit 1210 is complemented with a subsequent integrated circuit 1211 such as a graphics processor or radio frequency integrated circuit or both as determined in the description.
In one embodiment, the dual integrated circuit 1210 includes built-in fast access local memory 1217 such as eDRAM.
The dual integrated circuit 1211 includes a dual RFIC processor 1213 and a dual communications circuit 1215 and a fast dual access local memory 1217 such as SRAM.
In one embodiment, the dual communications circuit 1215 is particularly configured for RF processing.
In one embodiment, the at least one passive device 1280 is coupled to the subsequent integrated circuit 1211 so that the integrated circuit 1211 and the at least one passive device are part of any device modality that includes the TSV RFIC that corresponds to a PAA treatment with cavities that includes integrated circuit 1210 and integrated circuit 1211. 5 In one embodiment, electronics 1200 includes an antenna element 1282 just like any PAA modality determined in the description.
By using the antenna element 1282, as with any PAA mode determined in the description, a device of method 1284 such as a television, can be operated remotely over a wireless link by one mode of the apparatus.
For example, an application on a smart phone that operates through the TSV RFIC and PAA substrate with cavities sends instructions over a wireless link to a television up to about 30 meters away, such as using Bluetooth® technology. In one embodiment, the electronic system 1200 also includes an external memory 1240 which in turn can include one or more memory elements suitable for the particular application, such as a main memory 1242 in the form of RAM, one or more hard drives 1244, and / or one or more reading units that handle removable media 1246, such as floppy disks, compact discs (CDs), variable digital disks (DVDs), flash memory reading units, and other removable media known in the art.
In one embodiment, the external memory 1240 is stacked as a TSV chip between a mounting substrate and a PAA substrate with cavities according to any of the described modalities.
In one embodiment, external memory 1240 is built-in memory 1248 as well as a device that includes the TSV RFIC that corresponds to a PAA substrate with cavities according to any described modality.
In one embodiment, the 1200 electronic system also includes a 1250 display device, and a 1260 audio output. In one embodiment, the 1200 electronic system includes an input device such as a 1270 controller which can be a keyboard, mouse , touchpad, numeric keypad, trackball, game controller, microphone, voice recognition device, or any other input device that inputs the information
electronic system 1200. In one embodiment, an input device 1270 includes a camera.
In one embodiment, a 1270 input device includes a digital sound recorder.
In one embodiment, a 1270 input device includes a camera and a digital sound recorder. 5 A 1290 foundation substrate may be part of the 1200 computing system. In one embodiment, the 1290 foundation substrate is a motherboard that supports a device that includes the TSV RFIC that corresponds to a PAA substrate with cavities.
It can be understood that a low-cost secondary package can be part of the computer system 1200 as well as the motherboard on which the low-cost secondary package is mounted.
In the modality, the 1290 foundation substrate is a plate that supports an apparatus that includes the TSV RFIC that corresponds to a PAA substrate with cavities.
In one embodiment, the foundation substrate 1290 incorporates at least one of the features encompassed within the dotted line 1290 and is a substrate just like the user cartridge of a wireless communicator.
As shown here, the 1210 integrated circuit can be implemented in a number of different modalities, a device that includes the TSV RFIC which corresponds to a PAA substrate with cavities according to any of the various described modalities and their equivalents an electronic system, a computer system, one or more methods of making an integrated circuit, and one or more methods of making and assembling an apparatus that includes the TSV RFIC which corresponds to a PAA substrate with cavities according to any of the various modalities described as determined here in the various modalities and their equivalents recognized in the art.
The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit the particular needs of I / O coupling including a semiconductor substrate that is metallized with at least one self-forming barrier modality. self-aligned and their equivalents.
Although a stamping can refer to a processor chip, an RF chip, an RFIC chip, an IPD chip, or a memory chip can be mentioned in the same sentence, but it should not be constructed as being equivalent structures . References through the description of "the modality" or "a modality" mean that a particular characteristic, structure, or characteristics described in connection with the modality is included in at least one modality of the present invention. . The appearance of the phrases "in one modality" or "in modality" in various places throughout the present description are not necessarily all referring to the same modality. Furthermore, the particular characteristics, structures, or qualities can be combined in any suitable way in one or more modalities. Terms such as "top" and "bottom", "above" and "below" can be understood by reference to the illustrated XZ coordinates, and terms such as "adjacent" can be understood by reference to the XY coordinates or to non-Z coordinates. The summary is provided to meet 37 CFR §
1.72 (b) which requires a summary that will allow the reader to quickly verify the nature and essence of the technical description. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In the previous Detailed Description, several characteristics are grouped together in a single modality in order to simplify the description. Said description method should not be interpreted as reflecting an intention that the claimed embodiments of the present invention require more features than are expressly stated in each claim. Instead, as the following claims reflect, the purpose of the invention is based on less than all the characteristics of a single described modality. Thus the claims to be followed are hereby incorporated into the Detailed Description, with each claim remaining as a separate preferred modality. It will be readily understood by those skilled in the art that various other changes in details, materials, and arrangements of the parts and stages of the method that have been described and illustrated in order to explain the nature of the present invention can be produced without departing from the principles and scope of the present invention as expressed in the appended claims.

权利要求:
Claims (20)
[1]
1. In-phase antenna substrate (PAA), comprising: a first dielectric layer containing a plurality of emitting traces; 5 a second dielectric layer that corresponds to the first dielectric layer, in which the first dielectric layer has a higher dielectric constant than the second dielectric layer, in which the second dielectric layer is a glass and supports a structure of ante elements - na planes arranged on their top surface, and where the second dielectric layer includes a cavity structure that corresponds to the structure of flat antenna elements, in which each antenna element is vertically aligned with a corresponding cavity in one second dielectric layer.
[2]
2. PAA substrate according to claim 1, in which each flat antenna element has an area, and in which each corresponding cavity has the coverage area that is smaller than each corresponding area of antenna.
[3]
3. PAA substrate according to claim 1, in which each flat antenna element has an area, and in which each corresponding cavity has the coverage area which is equal to each corresponding antenna element area .
[4]
4. PAA substrate according to claim 1, in which each flat antenna element has an area, and in which each corresponding cavity has a coverage area that is larger than each corresponding antenna.
[5]
A PAA substrate according to claim 1, wherein each flat antenna element is covered on a bottom surface thereof with the second dielectric layer.
[6]
6. PAA substrate according to claim 1, wherein each flat antenna element is exposed on the bottom surface of the same by the corresponding cavity.
[7]
7. PAA substrate according to claim 1, in which each flat antenna element is disposed within a corresponding cavity and covered on the top surface of the same with the second dielectric layer.
[8]
8. Apparatus, comprising: 5 a wedge including a direct silicon path and an integrated radio frequency circuit (TSV RFIC wedge); and a phase antenna substrate (PAA) vertically integrated with a TSV RFIC, wherein the PAA substrate includes a first dielectric layer that supports at least one trace, wherein the PAA substrate includes a plurality of antenna elements arranged in a second dielectric layer of glass, each of which is coupled to the TSV RFIC through a plurality of TSVs, and each of which is arranged above the cavity, and in which the second dielectric layer is arranged in a first dielectric layer that supports at least one emitting trace.
[9]
Apparatus according to claim 8, in which each antenna element has an area, and in which the cavities have a coverage area that is smaller than the antenna element area.
[10]
Apparatus according to claim 8, in which each antenna element has an area, and in which the cavities have a coverage area that is equal to the area of the antenna element.
[11]
Apparatus according to claim 8, in which each antenna element has an area, and in which the cavities each have a coverage area that is larger than the antenna element area.
[12]
Apparatus according to claim 8, wherein the plurality of antenna elements on the PAA substrate is coupled to the TSV RFIC through inductive coupling openings on the PAA substrate.
[13]
Apparatus according to claim 8, wherein the plurality of antenna elements on the PAA substrate is coupled to the TSV RFIC via coupling on the PAA substrate.
[14]
Apparatus according to claim 8, additionally including: a first interconnected level substrate on which the
TSV RFIC is assembled, in which the PAA substrate includes an embedded ground plane coupled to the plurality of antenna elements and also coupled to the TSV RFIC; and at least one silent impact arranged between the 5 PAA substrate and the substrate on which the TSV RFIC is mounted.
[15]
Apparatus according to claim 8, additionally including: a direct silicon digital processor (TSV DP) wedge path coupled to the TSV RFIC via at least one TSV on the TSV RFIC and at least one TSV on the TSV DP , and where TSV DP and TSV RFIC are vertically integrated below the PAA substrate; a first interconnected level substrate on which the TSV DP is mounted, on which the PAA substrate includes an embedded ground plane coupled to the plurality of antenna elements and also coupled to the TSV RFIC; and at least one silent impact arranged between the PAA substrate and the substrate on which the TSV RFIC is mounted.
[16]
16. Apparatus according to claim 8, further including: a direct silicon memory wedge coupled to the TSV RFIC via at least one TSV in the TSV RFIC and at least one TSV in the TSV memory wedge, and wherein the TSV memory wedge and the TSV RFIC are vertically integrated below the PAA substrate; and a first interconnected level substrate on which the TSV memory slot is mounted, and in which a first interconnected level substrate includes at least one passive device embedded in it that works with the TSV RFIC.
[17]
17. The process of forming a vertically integrated apparatus comprising: forming a cavity in a glass substrate; form a phase structure antenna (PAA) element on the glass substrate above the cavity.
[18]
18. The method of claim 17, wherein each flat antenna element is formed to have covered the bottom surface of the same with the second dielectric layer.
[19]
19. The method of claim 17, wherein each flat antenna element is formed to be exposed on the bottom surface thereof by the corresponding cavity.
[20]
20. Method according to claim 17, in which each flat antenna element is formed to be disposed within the corresponding cavity and covered on the top surface thereof with the second dielectric layer.

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法律状态:
2020-08-18| B08F| Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]|Free format text: ARQUIVADO O PEDIDO DE PATENTE, NOS TERMOS DO ARTIGO 86, DA LPI, E ARTIGO 10 DA RESOLUCAO 113/2013, REFERENTE AO NAO RECOLHIMENTO DA 8A RETRIBUICAO ANUAL, PARA FINS DE RESTAURACAO CONFORME ARTIGO 87 DA LPI 9.279, SOB PENA DA MANUTENCAO DO ARQUIVAMENTO CASO NAO SEJA RESTAURADO DENTRO DO PRAZO LEGAL, CONFORME O DISPOSTO NO ARTIGO 12 DA RESOLUCAO 113/2013. |

2020-12-08| B08K| Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]|Free format text: EM VIRTUDE DO ARQUIVAMENTO PUBLICADO NA RPI 2589 DE 18-08-2020 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDO O ARQUIVAMENTO DO PEDIDO DE PATENTE, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013. |

2021-11-03| B350| Update of information on the portal [chapter 15.35 patent gazette]|

优先权:

申请号 | 申请日 | 专利标题

US13/101,891|US8901688B2|2011-05-05|2011-05-05|High performance glass-based 60 ghz / mm-wave phased array antennas and methods of making same|

US13/101,891|2011-05-05|

PCT/US2012/035421|WO2012151123A2|2011-05-05|2012-04-27|High performance glass-based 60 ghz / mm-wave phased array antennas and methods of making same|

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